Graduate Intern Technical - Logic Design null

Job description

In this position, you will be involved in the training design and development of next-generation Server SOCsCPUs. Your responsibilities will include some of the following but are not limited to assisting the design unit owners in Register Transfer Level RTL modeling amp functional validation. Use EDA tools extensively to simulate logic behavior and circuit performance and direction of physical design for next-generation deep submicron embedded circuit solutions. Verify the circuit behavior against the original simulation model and first silicon. Define VLSI Structural Design methodology and develop design flows. Implement structural physical designs such as synthesis floor planning power grid and clock tree designs timing budgeting and closure place and route RC extraction and integration. Verify structural physical designs such as functional equivalency timing performance noise layout design rules reliability and power.

Qualifications

You should be a student Postgraduate Masters ME, MTech, MS currently pursuing studies in a relevant field with a good understanding of semiconductor physics and basic PC architecture Additional qualifications include Familiarity with Very Large Scale Integration VLSI Complementary MetalOxide Semiconductor CMOS logic circuit design Well versed in UNIX C programming and relevant Computer-Aided Design CAD tools.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC and critical IPs to sustain Intel's Xeon and 5G networking roadmap.